Empleos de Timing Closure

Cisco's Silicon One Physical Design team is seeking an early-career Physical Design Engineer to contribute to backend ASIC implementation from RTL to GDS, including physical synthesis, place and…

ARQUIMEA is seeking a Backend ASIC/FPGA Engineer to own and execute backend implementation flows for ASIC and/or FPGA designs, including synthesis, place and route, timing closure, and mixed-signal…